(1) Field of the Invention
The present invention relates to a semiconductor device having another semiconductor device stacked thereon, and an inspection method of the semiconductor device.
(2) Description of the Related Art
In response to demand for small-sized, high-performance electronic apparatuses such as portable telephones and digital cameras, there is developed a stacking-type semiconductor module including electronic components, in particular, semiconductor chips integrated with each other in a stacked manner (refer to JP2004-363126A).
For example, a second semiconductor package containing a second semiconductor chip is stacked on a first semiconductor package containing a first semiconductor chip.
Such a stacking-type semiconductor module is subjected to an inspection after the aforementioned stacking process. Herein, a stacking-type semiconductor module evaluated as a defective is discarded. Alternatively, in the stacking-type semiconductor module evaluated as a defective, stacked packages must be disassembled from each other once and, then, must be assembled again. This leads to deterioration in yield.
In contrast, JP2004-281633A discloses a stacking-type module including a plurality of stacked chips. In the stacking-type module, each chip includes a mounting terminal used when the chip is mounted on a first single plane perpendicular to a stacking direction, and an inspecting terminal used when the stacking-type module is subjected to an inspection of quality. Each chip also includes a mounting pad connected to a mounting terminal of another chip adjacent to the chip on a second single plane different from the first single plane, and an inspecting pad electrically continuous with the inspecting terminal.
According to the aforementioned technique, first, an inspecting pad of a mounted chip is joined to an inspecting terminal of a chip to be stacked, and an inspection is performed in such a manner that an inspecting signal is input through an inspecting terminal, which is electrically continuous with the inspecting pad, of the mounted chip. Thereafter, if a result of the inspection is good, the chip to be stacked is allowed to move on a single plane on which the chip is mounted, and a mounting terminal of the chip to be stacked is connected to a mounting pad of the mounted chip.
Further, JP2002-83897A discloses a stacking-type semiconductor module readily subjected to an inspection of an electrical property. This module includes: a semiconductor chip; a substrate having a wiring pattern formed thereon, having the semiconductor chip mounted on one of faces thereof, and having an outer dimension larger than that of the semiconductor chip; a first terminal formed at a region, located outside a region where the semiconductor chip is mounted, in the substrate; and a second terminal partially containing the wiring pattern, and having a bared face opposite to a face opposing the semiconductor chip at a region located inside the region where the first terminal is formed in the substrate. Herein, the semiconductor chip is electrically connected to the first and second terminals.
In this semiconductor device, first and second terminals are electrically connected to a semiconductor chip, respectively. Thus, the first terminal can be used for an electrical connection with another member and the second terminal can be used for an inspection of an electrical property.
In addition, JP09-223725A discloses a semiconductor package of a grid array type. According to this semiconductor package, it is possible to readily perform an inspection of continuity between signal pins and a circuit pattern of a circuit board in a case that the semiconductor package is surface-mounted on the circuit board, and to readily perform an electrical test for the semiconductor package after completion of manufacturing. In the semiconductor package, a semiconductor device is surface-mounted on a circuit board in such a manner that signal pins are arranged on a bottom face thereof in form of a grid array and are joined to a circuit pattern of the circuit board. The semiconductor device includes a contact pad formed on a top face thereof and electrically connected to each signal pin.
According to the technique disclosed in JP2004-281633A, each chip to be stacked includes a mounting connection terminal and an inspecting connection terminal, and a substrate having each chip mounted thereon includes an inspecting joint and a mounting terminal used for a connection with another substrate. However, this stacking-type module has a configuration that the chip is directly mounted on the substrate. Consequently, a package in which a chip is mounted on a sub-substrate cannot be subjected to an inspection.
According to the technique disclosed in JP2002-83897A, an inspection can be performed by means of a second terminal. However, a connection terminal used for stacking cannot be subjected to an inspection.
According to the technique disclosed in JP09-223725A, an inspection of continuity can be performed by means of a signal pin and a contact pad. However, if this technique is applied to a stacking-type semiconductor module, a contact pad to be used as a stacking connection terminal is damaged due to contact with a probe. Consequently, connection failure readily occurs.
On the other hand, as an electronic apparatus is reduced in size and thickness and a semiconductor chip is reduced in thickness, there is increasingly demanded enhancement in function in such a manner that semiconductor chips are stacked. In addition, a semiconductor device having semiconductor chips stacked thereon is realized as follows. That is, there are prepared a plurality of semiconductor chips to be stacked, and semiconductor chips to be mounted are selected in accordance with application. In this case, a semiconductor device to be stacked must be subjected to an inspection of a connection status between terminals in order to secure reliability before semiconductor chips are stacked on the semiconductor device. For example, in an inspection of interconnection in a semiconductor device before stacking, it is necessary to inspect a status of electrical continuity between a connection terminal provided for a connection with a semiconductor device to be mounted on the semiconductor device and a bump electrode provided for a connection with an external apparatus. In this inspection method, a probe is used as disclosed in JP09-223725A. In this method, however, a contact pad is damaged as described above, so that connection failure readily occurs. Further, a tester to be used herein is expensive.